Patterned wafers provided for chip production cannot, in practice, be produced without deviations from the ideal pattern. The surface extent of deviations that can negatively affect the functionality of a chip is in the micrometer range. Pattern defects of this kind can be detected, for example, under a microscope.
Deviations can, for example, be classified as to whether or not they make a chip unusable. There may be deviations that cause the chip to be unusable because of their position and characteristics even if they occur only individually. On the other hand, even a larger number of deviations may have no effect on the functionality of the chip.
Automatic examination methods which check, field by field, a chip that has been divided into a plurality of individual image fields, are used to detect the deviations. Given the large number of individual image fields that each contain a large quantity of detailed image data, the high information density means that the amount of data generated cannot be processed quickly enough by computer. Instead, online inspection methods confine themselves initially to the question of whether or not any deviation at all is evident in an individual image field. The comparison is made not to a reference image, but by comparison with a chip or wafer examined immediately previously. The reason this is practical is that the number of random deviations is very small in relation to the number of image points to be examined. Systematic deviations cannot, however, be detected in this fashion.
If the decision as to whether to discard a wafer is to be made not solely as a function of statistically predetermined limit values, it is then necessary to examine those individual images affected by a deviation once again “offline,” in a further operation, by removing the wafer in question from the production line. For that purpose, the individual image fields affected by deviations must once again be looked at, in very time-consuming fashion, and individually evaluated by a person; although that person can in some cases utilize preformulated decision rules, he or she must nevertheless often rely on personal examination experience, and in some cases also decide intuitively.
Many of the deviations examined will turn out to be noncritical pseudo-defects, while the risk remains that a critical deviation will be regarded as a harmless pseudo-defect. The relevance of the conclusions reached in this manner, in terms of the decision as to whether a wafer can be released for further processing or must be discarded, is therefore unsatisfactory.
As the technical development of computer chips has proceeded, there has been a continuing miniaturization of surface patterns which is beginning to move away from the microscopically observable realm, so that consequently even smaller deviations become relevant in terms of disruption, and the inspection methods utilized previously are no longer sufficient.
The greater resolution of the individual image fields that is thus also necessary moreover results in a further increase in the image data required for an assessment. There is moreover a tendency toward the use of chips with a greater overall surface area. This, too, is associated with an additional increase in image data, and is incompatible with extensive defect evaluation in the context of automatic defect monitoring in a wafer production line.
In addition, production-engineering aspects must also be considered in the context of wafer defect monitoring methods. For example, a production line for manufacturing wafers should, if possible, never shut down. If, in the context of a continuous examination, each pseudo-defect were to trigger a discard operation for the wafer in question, then a continuous production process would be unimaginable, since practically every wafer exhibits such pseudo-defects.
If an attempt were made with previously known means to perform “online” automated defect evaluation on the basis of the acquired image data for each individual image field that went beyond a yes/no decision in terms of the presence of a deviation, the outlay in terms of computing technology would be immense and would far exceed present-day capabilities.
U.S. Pat. No. 5,825,482, for example, describes a surface inspection system in which a comparison is made with reference data, in which context defects on patterned wafers can be found. The result of the inspection is to provide “wafer plots” which must be interpreted by the operator in terms of process deviations. Automatic evaluation or even classification of identified defects is neither possible nor even provided for.
U.S. Pat. No. 5,173,719 discloses a system which takes into account the fact that circuits have areas with repetitive patterns, and with which both the usual chip comparison and an inspection of the repetitive patterns can be performed simultaneously. For the chip comparison, some of the data are read into a delay-line memory and then compared to the adjacent chip. The inspection of repetitive patterns is accomplished similarly, but the volume of data to be taken into account is much smaller. Two inspection channels operate simultaneously, window control being used for differentiation. Here again, no classification of defects is performed.
U.S. Pat. No. 5,544,256 describes in detail a system that is configured for post-classification of defect locations that have already been found. The basis used is a label image that is calculated from a defect-free reference image. This requires disproportionately high computing performance, with the result that classification proceeds extraordinarily slowly and this system is not suitable for a rapid production sequence.
The aforementioned method is embodied further in U.S. Pat. No. 5,808,735. Here, in order to reduce the false-alarm rate in the classification of defects, a three-dimensional image-to-image comparison is performed. The reference image is described by an array of image points, each image point having defined X-Y-Z coordinates and a defined intensity. The image points of a specific image plane are grouped, and a threshold value is defined therewith. A rapid classification pace can nevertheless be achieved only by limiting the inspection to selected portions of the wafer, so that here again the preconditions for use in a process line are only insufficiently present.
U.S. Pat. No. 5,699,447 presents a two-phase optical method for rapid inspection of all critical layers at a low pseudo-defect rate. In a first phase, the wafer is quickly scanned with a laser, while in the second phase, the locations identified in the first phase as possibly defect-affected are looked at, along with a reference pattern. Images are then generated in various focal planes in order to confirm or rule out the existence of a defect. This procedure is also relatively time-consuming.
To decrease the time expenditure, U.S. Pat. No. 5,659,630 proposes an inspection system in which a binary reference image is generated from the CAD pattern data. The continuous original image of the pattern being examined is binarized, and the two images are then subjected to a specific comparison for each defect type. The disadvantages are on the one hand the fact that signal processing is still too slow, and on the other hand the hardware and software outlay necessary for each individual defect type. This system also possesses only limited variability, since the hardware for new defect types cannot readily be programmed.
U.S. Pat. No. 5,801,965 presents a system and a method in which defect detection and defect classification are integrated into a process control system. The system uses two measuring instruments, however, and thus also possesses the disadvantages already cited.